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November 2013
SSN1N45B
N-Channel B- FET
450 V, 0.5 A, 4.25 ?
Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology. This advanced technology has
been especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand
high energy pulse in the avalanche and commutation
mode. These devices are well suited for electronic ballasts
based on half bridge configuration.
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0.5 A, 450 V, R DS(on) = 4.25 ? @ V GS = 10 V
Low G ate C harge (typical 6.5 nC)
Low Crss ( t ypical 6.5 pF)
100% A valanche T ested
Improved dv/dt C apability
Gate-Source Voltage ± 50V G uaranteed
D
G
D
S
TO-92
G
S
= 25 C unless otherwise noted.
Absolute Maximum Ratings T
C
o
Symbol
V DSS
Drain-Source Voltage
Parameter
SSN1N45B TA
450
Unit
V
I D
Drain Current
- Continuous (T C = 25°C)
- Continuous (T C = 100°C)
0.5
0.32
A
A
I DM
Drain Current
- Pulsed
(Note 1)
4.0
A
V GSS
Gate-Source Voltage
± 50
V
E AS
I AR
E AR
dv/dt
P D
T J , T stg
T L
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T A = 25°C)
Power Dissipation (T L = 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum L ead T emperature for S oldering,
1/8 " from C ase for 5 S econds
(Note 2)
(Note 1)
(Note 1)
(Note 3)
108
0.5
0.25
5.5
0.9
2.5
0.02
-55 to +150
300
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Thermal Characteristics
Symbol
Parameter
SSN1N45BTA
Unit
R θ JL
R θ JA
Thermal Resistance, Junction-to-Lead , Max.
Thermal Resistance, Junction-to-Ambient , Max.
(Note 5 a)
(Note 5 b)
50
140
°C / W
°C / W
?2002 Fairchild Semiconductor Corporation
SSN1N45B Rev. C 0
1
www.fairchildsemi.com
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